1. Field of the Invention
The present invention relates to a bus system of a semiconductor device arranged in an LSI (Large-Scale Integrated Circuit) and, more particularly, to a bus system of a semiconductor device to which a plurality of circuits having different bit ranges are connected.
2. Description of the Related Art
FIG. 1 is a block diagram showing a bus system arranged in a conventional semiconductor device. A bus wiring line 71 has a 16-bit range. 16-bit registers 721-1 to 721-4 each having the same bit range as that of the bus wiring line 71 are connected to the bus wiring line 71. An external input/output bidirectional buffer circuit 73 having a 16-bit range which is the same as that of the bus wiring line 71 is connected to the bus wiring line 71. 8-bit registers 741-1 to 741-4 each having a bit range which is half the bit range of the bus wiring line 71 is connected to the lower 8 bits (A0 to A7). With the above arrangement, the fan-in counts and fan-out counts of the circuits connected to the bus wiring line 71 are compared with each other. That is, the four registers 721-1 to 721-4 and the buffer circuit 73 (total five circuits) are connected to the upper 8 bits (A8 to A15) of the bus wiring line 71. In addition to the above five circuits, the four registers 741-1 to 741-4, i.e., total 9 circuits, are connected to the lower 8 bits (A0 to A7) of the bus wiring line 71. Therefore, the upper 8 bits and lower 8 bits of the bus wiring line 71 are different from each other in load, i.e., the wiring capacity of the bus wiring line 71 is different from the gate capacity of the MOS transistors of the circuits. In this manner, the bus wiring line 71 has variations in load in units of bits. When the registers connected to the bus wiring line 71 have he same structure and data transfer operations between the registers, for example, is performed, times required for the data transfer operations are different from each other due to the variations in load of the bus wiring line.
FIGS. 2(a) to 2(c) are timing charts showing the operations of the circuits connected to the bus wiring line when data is transferred from, e.g., the 16-bit register 721-1 to the 16-bit register 721-4. 16-bit data D1 stored in the 16-bit register 721-1 is output to the bus wiring line 71 in synchronization with rise time t1 of a clock signal CLK. In this case, since the load of the lower 8 bits (A0 to A7) of the bus wiring line 71 is larger than that of the upper 8 bits (A8 to A15), the 16-bit data D1 is transferred up to the input of the 16-bit register 721-4. The speed of data D1a of the lower bits is lower than that of data D1b of the upper bits, and the transfer times of the data D1a and D1b have a difference .DELTA.t. As a result, the data transfer speed of the bus wiring line 71 depends on the lower 8 bits having the lower speed. The data D1 is stored in the 16-bit register 721-4 in synchronization with rise time t2 of the clock signal CLK. If the lower 8 bits (A0 to A7) have the same speed as that of the upper 8 bits (A8 to A15), the duty cycle of the clock signal CLK can be increased to the operating speed of the upper 8 bits. That is, since the duty cycle of the clock signal CLK is determined depending on data having a minimum transfer speed and selected from the data of the bus wiring line 71, the operating frequency of the clock signal CLK cannot be increased. As a result, the operating frequency which influences the performance of the system is limited.